The present invention generally relates to xDSL communications. More specifically, the invention relates to analog front ends (AFES) for VDSL communication.
With the advancement of technology, and the need for instantaneous information, the ability to transfer digital information from one location to another, such as from a central office to customer premises, has become more and more important.
In a digital subscriber line (DSL) system, data is transmitted from a central office to customer premises via a transmission line, such as a two-wire pair, and is transmitted from the customer premise to the central office as well, either simultaneously or in different communication sessions. The same transmission line might be utilized for data transfer by both sites or the transmission to and from the central office might occur on two separate lines. In its most general configuration, a DSL card at a central office is comprised of a digital signal processor (DSP) which receives information from a data source and sends information to an analog front-end (AFE). The AFE serves as the interface between an analog line, such as the two-wire pair, and the DSP. The AFE functions to convert digital data, from the DSP, into a continuous-time analog signal when processing downstream data. Conversely, the AFE serves to convert an analog signal to digital data when processing upstream data.
As an important part of the aforementioned system responsible for proper transmission and reception of data in a broadband network, the AFE performs multiple functions in addition to converting a digital signal into a continuous time analog signal, and vice versa. However, the functionality of the AFE is particular to the specific DSL application considered, wherein factors such as signal bandwidth, data rate, data reach, signal quality, power budget, and different applicable standards determine the optimum AFE. In order to minimize application specific implementations of digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) across the many DSL applications, it is desired to create high-performance configurable DACs and ADCs.
Asynchronous DSL (ADSL) is a popular service provided for residential customers, due to the asymmetrical nature of data usage, wherein more data flows towards the customer in the downstream direction, in comparison to the upstream data flow. The larger downstream data flow is generally attributed to accessing Internet Web sites. When a Web site is accessed, a relatively large amount of data related to the Web page is transmitted downstream to a browser located in a customer""s PC. The bulk of the upstream data is generally attributable to e-mail traffic directed towards other Internet users, and this constitutes a smaller data volume than the one traveling downstream.
Very High bit-rate DSL (VDSL) is similar to ADSL but provides large amounts of bandwidth with speeds up to about 52 Mbps. In order to provide such high speeds, a large bandwidth, as mentioned, is required. Typically, the VDSL frequency band ranges from 300 kHz to up to about 12 MHz. Unfortunately, the trade-off with high frequencies is the distance the signals can travel along a copper line. The development of Fiber to the Curb (FTTC) and/or Fiber to the Neighborhood (FTTN) provides for the use of VDSL by, essentially, reducing the length of the copper loop. Fiber cables, which can support high bandwidths over long distances, are provided from the CO to Optical Network Units (ONUs) located either at the curb of residences or the gateway to a neighborhood. The ONUs can convert the optical signals into electrical signals downstream and vice-versa upstream. With the use of FTTN and or FTTC, the effective copper loop is reduce to below 4000 ft, which is the upper limit of VDSL. VDSL, for example, provides for the transmission of video signals over copper lines, which leads to applications such as digital television, Video-on-Demand, etc.
Traditional AFEs for ADSL cannot be utilized for VDSL applications because of the bandwidth issues and the high frequencies involved. In particular, the ADC located in the upstream signal path of a CO AFE is affected by the high-frequency signal. Improvements of the ADC for high-frequency applications includes pipeline structures. The oversampling ADC is usually not suitable for VDSL because of the bandwidth requirements. VDSL requires about 10 times the bandwidth of ADSL. For example, for a typical ADC for ADSL the oversampling ratio is usually 32, which equates to a clock frequency of about 71 MHz. If this same structure is used for VDSL, the clock frequency would be more than 700 MHz. Using an ADC pipeline structure, the clock frequency may be only 2 times the bandwidth. To help in filter designs, however, the clock frequency is typically 3 to 4 times the bandwidth. For VDSL applications this is much lower than what the oversampled approach would provide. Unfortunately, high-speed ADCs have caused a need for associated drive amplifiers or buffers to be placed at the input of the ADCs. Typically, the buffers must provide a low source impedance and sufficient instantaneous output current to drive the ADC, and its high-frequency output impedance must be sufficiently low to avoid excessive conversion error.
Switched capacitance (SC) architectures for ADCs have added drawbacks in that a large transient spike of input current is drawn at the end of each conversion, when the internal sampling capacitors switch back to the input for acquisition of the next sample. To avoid error, the buffer circuitry must recover from this transient and settle before the next conversion starts. This helps avoid the xe2x80x9ckick-backxe2x80x9d affect caused by the transient on the preceeding continuous-time blocks in the receive path of the AFE.
One prior-art solution to the problem caused by SC ADCs is to utilize a standard unity-gain buffer and add an RC filter prior to the buffer stage. The capacitor of the RC filter would typically be much larger than the ADC""s input capacitance, which helps to eliminate the transient by providing charge for the sampling capacitor. Unfortunately, RC filtering is only effective when oversampled ADCs are utilized and where the signal bandwidth is much smaller than the clock frequency. Without oversampling, a single-pole filtering is not effective especially considering the large cut-off frequency variation of the RC filter.
Another problem with this general configuration is the input nonlinear parisitic capacitance of the buffer. If the driving impedance is high, distortion tends to be the result. Using an RC filter increases the impedance seen by the ADC buffer input unless the resistance of the RC filter is small. If the resistance is small, the capacitance that creates the pole of the RC filter will load the continuous-time blocks, which can significantly degrade performance and cause instability.
Therefore, there exists a need for improved ADC buffers and AFEs for high frequency applications, such as VDSL. It would also be desirable for this solution to be readily configured for other applications, such as other xDSL applications.
The present invention relates to improved ADC buffers and AFEs for high-frequency applications, such as VDSL. The present invention can also be programmably configured for other xDSL applications. In this regard, a buffer circuit for a high-bandwidth analog-to-digital converter (ADC) includes a first unity-gain buffer configured to receive an analog input signal. The first unity-gain buffer includes a MOSFET differential amplifier with a current mirror load and a transient-reduction network electrically interconnected with the MOSFET differential amplifier and configured to reduce transient energy emitted by the ADC. The buffer circuit also includes a second unity-gain buffer cascaded to the first unity-gain buffer and configured to provide the analog input signal from the first unity-gain buffer to the ADC.
In another embodiment, the invention may be construed to be an AFE for a communication system. The AFE comprising, in its receive path at least a first continuous-time processing element, a dual-stage ADC buffer coupled to the at least first continuous-time processing element, and a Nyquist switched-capacitance (SC) ADC coupled to the ADC buffer.